`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/07/31 12:41:05
// Design Name: 
// Module Name: inst_decode
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module inst_decode(
    clk,reset_n,nop_b,nop_j,inst,rd_wb,data_wb,data_1,data_2,op_imm,imm_1,imm_2,imm_3,imm_4,rd_id,op_wr,op_rd,op_rd_mem,op_alu,op_b,op_j,
    addr_next_if,addr_next_id,opcode_id,fw_1,fw_2,lu,opcode_exe,rd_exe_fw,rd_mem_fw,nop_fw
    );
    input clk,reset_n,nop_b,nop_j;
    input [4:0] rd_exe_fw,rd_mem_fw,rd_wb;
    input [31:0] inst;
    input [31:0] data_wb;
    input [1:0] op_rd_mem;
    input [31:0] addr_next_if;
    input [6:0] opcode_exe;
    output [2:0] op_imm;
    output [31:0] data_1,data_2;
    output reg [31:0] addr_next_id;
    output [4:0] imm_1;
    output [11:0] imm_2;
    output [6:0] imm_3;
    output [19:0] imm_4;
    output [6:0] opcode_id;
    output [4:0] rd_id;
    output [1:0] op_wr;
    output [1:0] op_rd;
    output [2:0] op_alu;
    output op_b,op_j;
    output lu,nop_fw;
    output [1:0] fw_1,fw_2;

    wire [6:0] opcode;
    wire [4:0] rs1,rs2;
    wire [2:0] funct3;
    wire [6:0] funct7;
    wire nop;
    
    assign nop = nop_j || nop_b;

    always @(posedge clk) begin
        if(nop) begin
            addr_next_id <= 32'bx;
        end
        else begin
            addr_next_id <= addr_next_if;
        end
    end

    decode decode(.clk(clk),.nop(nop),.inst(inst),.rs1(rs1),.rs2(rs2),.rd(rd_id),.opcode(opcode),.funct3(funct3),.funct7(funct7),.imm_1(imm_1),
    .imm_2(imm_2),.imm_3(imm_3),.imm_4(imm_4),.opcode_id(opcode_id));
    registers registers(.clk(clk),.nop(nop),.reset_n(reset_n),.rs1(rs1),.rs2(rs2),.rd(rd_wb),.data(data_wb),.data_1(data_1),.data_2(data_2),
    .op_rd(op_rd_mem));
    cu cu(.clk(clk),.nop(nop),.opcode(opcode),.funct3(funct3),.funct7(funct7),.op_imm(op_imm),.op_wr(op_wr),.op_rd(op_rd),.op_alu(op_alu),
    .op_b(op_b),.op_j(op_j));
    forward forward(.clk(clk),.rs1(rs1),.rs2(rs2),.rd_exe(rd_exe_fw),.rd_mem(rd_mem_fw),.opcode_exe(opcode_exe),.lu(lu),
    .fw_1(fw_1),.fw_2(fw_2),.nop_fw(nop_fw));

endmodule
